Advantages of MIPI data transmission as display interface

   With the advent of the global 5G and AI smart era, the performance of CPU chips in hardware products has greatly improved, and the requirements for LCD screen interfaces have also increased. The demand for MIPI high-speed transmission interfaces is increasing. After a long period of research and development and increased investment, our company We have launched a variety of MIPI interface displays, ranging from 1.14 inches to 10.1 inches, with MIPI interfaces for customers to choose from, meeting the needs of our customers for small and medium-sized MIPI interface LCD screens.

   MIPI is specifically tailored for power-sensitive applications using low-amplitude signal swings in high-speed (data transfer) mode. 

   Since MIPI uses differential signal transmission, the design needs to be strictly designed in accordance with the general rules of differential design. The key is to achieve differential impedance matching. The MIPI protocol stipulates that the differential impedance value of the transmission line is 80-125 ohms.

    MIPI is specifically tailored for power-sensitive applications using low-amplitude signal swings in high-speed (data transfer) mode.

    Since MIPI uses differential signal transmission, the design needs to be strictly designed in accordance with the general rules of differential design. The key is to achieve differential impedance matching. The MIPI protocol stipulates that the differential impedance value of the transmission line is 80-125 ohms.

  MIPI specifies a differential clock channel (lane) and a scalable number of data lanes from 1 to 4, which can adjust the data rate according to the needs of the processor and peripherals. Moreover, the MIPI D-PHY specification only gives a data rate range and does not specify a specific operating rate. In an application, the available data channels and data rates are determined by the devices on both sides of the interface. However, the MIPI D-PHY IP core currently available can provide transfer rates of up to 1 Gbps per data lane, which undoubtedly means that MIPI is fully suitable for current and future high-performance applications.

   There is another big benefit to using MIPI as the data interface. MIPI is ideally suited for new smartphone and MID designs because the MIPI DSI and CSI-2 architectures bring flexibility to new designs and support compelling features such as XGA displays and higher-than-8-megapixel cameras. With the bandwidth capabilities offered by new MIPI-enabled processor designs, it is now possible to consider leveraging a single MIPI interface to enable novel features such as high-resolution dual-screen displays and/or dual cameras.

    In designs incorporating these features, high-bandwidth analog switches designed and optimized for MIPI signals, such as Fairchild Semiconductor's FSA642, can be used to switch between multiple display or camera components. The FSA642 is a high-bandwidth three-way differential single-pole double-throw (SPDT) analog switch that can share one MIPI clock channel and two MIPI data channels between two peripheral MIPI devices. Such switches can provide some additional advantages: isolation of spurious signals (stubs) from unselected devices and increased flexibility in routing and peripheral placement. To ensure the successful design of these physical switches on the MIPI interconnect path, in addition to bandwidth, some of the following major switch parameters must be considered:

1. Off isolation: In order to maintain the signal integrity of the active clock/data path, the switch is required to have efficient off isolation performance. For high-speed MIPI differential signals at 200mV and a maximum common-mode mismatch of 5mV, the off isolation between switch paths should be -30dBm or better.

2. Differential delay difference: The delay difference (skew) between the signals within the differential pair (the intra-differential pair delay difference) and the delay difference between the differential intersection points of the clock and data channels (the inter-channel delay difference) must be reduced to 50 ps or more. Small. For these parameters, the industry's best-in-class delay differential performance for this type of switch is currently between 20 ps and 30 ps.

3. Switch impedance: The third major consideration when selecting an analog switch is the trade-off between the impedance characteristics of on-resistance (RON) and on-capacitance (CON). The MIPI D-PHY link supports both low-power data transmission and high-speed data transmission modes. Therefore, the RON of the switch should be chosen in a balanced way to optimize the performance of the mixed operating mode. Ideally, this parameter should be set separately for each operating mode. Combining the optimal RON for each mode and keeping the switching CON very low is important to maintain the slew rate at the receiver. A general rule is that keeping CON below 10 pF will help avoid deterioration (lengthening) of the signal transition time through the switch in high-speed mode.

   Compared with parallel ports, MIPI interface modules have the advantages of fast speed, large amount of data transmission, low power consumption, and good anti-interference. They are increasingly favored by customers and are growing rapidly. For example, an 8M module with both MIPI and parallel port transmission requires at least 11 transmission lines and an output clock of up to 96M to achieve 12FPS full pixel output when using 8-bit parallel port transmission. However, using the MIPI interface only requires 2 A channel of 6 transmission lines can achieve a frame rate of 12FPS under full pixels, and the current consumption will be about 20MA lower than parallel port transmission. Since MIPI uses differential signal transmission, the design needs to be strictly designed in accordance with the general rules of differential design. The key is to achieve differential impedance matching. The MIPI protocol stipulates that the differential impedance value of the transmission line is 80-125 ohms.